1. Field of the Invention
The present invention relates generally to dielectric layers formed within microelectronics fabrications. More particularly, the present invention relates to barrier dielectric layers formed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics fabrication integration levels have increased and microelectronics fabrication device and patterned conductor layer dimensions have decreased, it has become increasingly more important to form within microelectronics fabrications narrow linewidth dimension and/or narrow pitch dimension microelectronics devices and patterned microelectronics conductor layers which have formed interposed therebetween void free, gap filling and planarizing microelectronics dielectric layers.
Of the methods which may be employed for forming void free, gap filling and planarizing microelectronics dielectric layers interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimensions microelectronics devices and patterned microelectronics conductor layers within microelectronics fabrications, high density plasma chemical vapor deposition (HDP-CVD) methods have recently received increased attention. High density plasma chemical vapor deposition (HDP-CVD) methods are characterized as plasma enhanced chemical vapor deposition (PECVD) methods undertaken simultaneously with sputtering methods, where the deposition rates within the plasma enhanced chemical vapor deposition (PECVD) methods are greater than that sputtering rates within the sputtering methods. Such high density plasma chemical vapor deposition (HDP-CVD) methods typically employ plasma enhanced chemical vapor deposition (PECVD) methods as are generally known in the art of microelectronics fabrication, typically undertaken simultaneously with bias sputtering methods employing argon sputtering ions. Dielectric materials which may be formed into dielectric layers while employing high density plasma chemical vapor deposition (HDP-CVD) methods include but are not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials.
Although high density plasma chemical vapor deposition (HDP-CVD) methods are thus desirable within the art of microelectronics fabrication for forming void free, gap filling and planarizing dielectric layers interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension microelectronics devices or patterned microelectronics conductor layers within microelectronics fabrications, high density plasma chemical vapor deposition (HDP-CVD) methods are not entirely without problems when forming void free, gap filling and planarizing dielectric layers within microelectronics fabrications. In particular, due to the intensity of a bias sputtering component typically employed within a high density plasma chemical vapor deposition (HDP-CVD) method, microelectronics devices and/or patterned microelectronics conductor layers formed beneath dielectric layers formed employing high density plasma chemical vapor deposition (HDP-CVD) methods often sustain high density plasma induced degradation incident to forming those high density plasma chemical vapor deposited (HDP-CVD) dielectric layers. The high density plasma induced degradation may be evidenced as either physical damage to, or compromised operating parameters of, patterned microelectronics conductor layers or microelectronics devices formed beneath those high density plasma chemical vapor deposited (HDP-CVD) dielectric layers.
It is thus towards the goal of forming within microelectronics fabrications high density plasma chemical vapor deposited (HDP-CVD) dielectric layers with attenuated degradation of microelectronics devices and patterned microelectronics conductor layers fabricated beneath those high density plasma chemical vapor deposited (HDP-CVD) dielectric layers incident to forming those high density plasma chemical vapor deposited (HDP-CVD) dielectric layers that the present invention is directed.
Various methods have been disclosed in the art of microelectronics fabrication for forming dielectric layers with desirable properties within microelectronics fabrications.
For example, Cheng, in ULSI Technology, Chang et al., eds., Mc-Graw-Hill (New York: 1996), pp. 260-61, discloses both a conventional spin-on-glass (SOG) method for forming within an integrated circuit microelectronics fabrication a planarizing inter-metal dielectric (IMD) layer and an electron cyclotron resonance chemical vapor deposition (ECR-CVD) high density plasma chemical vapor deposition (HDP-CVD) method for forming within an integrated circuit microelectronics fabrication a planarizing inter-metal dielectric (IMD) layer.
In addition, Jain et al., in U.S. Pat. No. 5,494,854, discloses a method for forming with enhanced throughput, gap-filling capability, planarity and uniformity within a microelectronics fabrication a chemical mechanical polish (CMP) planarized dielectric layer upon a patterned conductor layer whose conductor patterns are of varying aspect ratio. The method employs a high density plasma chemical vapor deposition (HDP-CVD) method to form a first dielectric layer which planarizes the high aspect ratio, but not necessarily the low aspect ratio, conductor patterns within the patterned conductor layer, where the first dielectric layer subsequently has formed thereupon a second dielectric layer formed of a dielectric material which is more readily planarized within the chemical mechanical polish (CMP) method than the first dielectric layer.
Further, Lee, in U.S. Pat. No. 5,605,859, discloses an insulator structure for use within an integrated circuit microelectronics fabrication, where the insulator structure maintains the integrity of a polysilicon resistor formed within the insulator structure within the integrated circuit microelectronics fabrication. The insulator structure employs a silicon oxide dielectric layer formed as a barrier layer interposed between the polysilicon resistor and an overlying dielectric layer formed within the integrated circuit microelectronics fabrication, where the silicon oxide dielectric layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing silane as a silicon source material.
Finally, Wang et al., in U.S. Pat. No. 5,679,606, discloses an electron cyclotron resonance high density plasma chemical vapor deposition (ECR-HDP-CVD) method for forming with attenuated patterned conductor layer damage an electron cyclotron resonance high density plasma chemical vapor deposited (ECR-HDP-CVD) dielectric layer upon a patterned conductor layer within a microelectronics fabrication. Within the method, an argon flow employed within a sputtering component within the electron cyclotron resonance high density plasma chemical vapor deposition (ECR-HDP-CVD) method is cycled off and on to form an initial deposit of an electron cyclotron resonance chemical vapor deposited (ECR-CVD) silicon oxide dielectric layer, but not an electron cyclotron resonance high density plasma chemical vapor deposited (ECR-HDP-CVD) dielectric layer, in order to attenuate patterned conductor layer damage when forming the electron cyclotron resonance high density plasma chemical vapor deposited (ECR-HDP-CVD) dielectric layer upon the patterned conductor layer.
Desirable in the art of microelectronics fabrication are additional methods for forming high density plasma chemical vapor deposited (HDP-CVD) dielectric layers with attenuated degradation to microelectronics devices and patterned microelectronics conductor layers formed beneath those high density plasma chemical vapor deposited (HDP-CVD) dielectric layers incident to forming those high density plasma chemical vapor deposited (HDP-CVD) dielectric layers. It is towards that goal that the present invention is directed.